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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12509-4E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89120/120A Series
MB89121/P131/123A/P133A/125A/P135A/PV130A
s OUTLINE
The MB89120 series is a line of single-chip microcontrollers containing a compact instruction set and a great variety of peripheral functions such as a timer, serial interface, and external interrupt. The MB89120A series is an extended variant of the MB89120, with a remote control transmission function and wake-up interrupt channels.
s FEATURES
* * * * * * * * * * * * * * F2MC-8L family CPU core Low-voltage operation Low current consumption (allowing for dual clock) Minimum execution time: 0.95 s at 4.2 MHz 21-bit timebase counter I/O ports: Max. 36 ports External interrupts: 3 channels External interrupts (wake-up function): 8 channels (only in the MB89120A series) 8-bit serial I/O: 1 channel 8-/16-bit timer/counter: 1 channel Built-in remote-control transmitting frequency generator (only in the MB89120A series) Low-power consumption modes (stop mode, sleep mode, watch mode) Package: QFP-48 CMOS technology
s PACKAGE
48-pin Plastic QFP
(FPT-48P-M13)
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MB89120/120A Series
s PRODUCT LINEUP
Part number
MB89121
Item
MB89123A Mass-produced products (Mask ROM products)
MB89125A
MB89P133A
MB89P131
Classification ROM size
One-time products 8 K x 8 bits (Internal PROM to be programmed with a generalpurpose EPROM programmer) 4 K x 8 bits (Internal PROM to be programmed with a generalpurpose EPROM programmer) 128 x 8 bits
4 K x 8 bits (internal mask ROM)
8 K x 8 bits (internal mask ROM)
16 K x 8 bits (internal mask ROM)
RAM size CPU functions
128 x 8 bits
256 x 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.95 s at 4.2 MHz 8.57 s at 4.2 MHz
The number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Minimum interrupt processing time: Output ports (N-ch open-drain): Output ports (CMOS): I/O ports (CMOS): Total:
Ports
4 (All also serves as peripherals.) 8 24 (8 ports also serve as peripherals.) 36
8/16-bit timer/counter 8-bit serial I/O External interrupt 1 External interrupt 2 (wake-up function) Remote control transmitting frequency generator Standby mode Process Operating voltage* EPROM for use
8-bit timer/counter x 2 channels or 16-bit event counter x 1 channel 8 bits LSB/MSB first selectable 3 Independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge/both edges selectable Also for wake-up from stop/sleep mode (edge detection is also permitted in stop mode) -- 8 channels (only for level detection) --
--
1 channel (pulse width and frequency selectable by program) Sleep mode, stop mode, watch mode CMOS
--
2.2 V to 4.0 V (with the dual clock option) 2.2 V to 6.0 V (with the single clock option) -- -- -- --
2.7 V to 6.0 V --
* : Varies with conditions such as operating frequencies. (See "s Electrical Characteristics.")
(Continued)
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MB89120/120A Series
(Continued)
Part number Item
MB89P135A One-time PROM products 16 K x 8 bits (internal PROM, to be programmed with general-purpose EPROM programmer) 512 x 8 bits The number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Minimum interrupt processing time: Output ports (N-ch open-drain ports): Output ports (CMOS): I/O ports (CMOS): Total:
MB89PV130A Piggyback/evaluation product 32 K x 8 bits (external ROM) 1 K x 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.95 s/4.2 MHz 8.57 s/4.2 MHz 4 (All also serve as peripherals.) 8 24 (8 ports also serve as peripherals. For MB89130A, 16 ports also serve as.) 36
Classification ROM size
RAM size CPU functions
Ports
8/16-bit timer/ counter 8-bit serial I/O External interrupt 1
8-bit timer/counter x 2 channels or 16-bit event counter x 1 channel 8 bits LSB/MSB first selectable 3 independent channels (edge selection, interrupt vector, source flag) Rising/falling/both edges selectable Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) 8 channels (only for level detection) 1 channel (Pulse width and cycle selectable by program) Sleep mode, stop mode, and clock mode CMOS 2.7 V to 6.0 V -- 2.7 V to 6.0 V MBM27C256A-20TVM
External interrupt 2 (wake-up function) Remote control transmitting frequency generator Standby mode Process Operating voltage* EPROM for use
* : Varies with conditions such as operating frequencies. (See "s Electrical Characteristics.")
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MB89120/120A Series
s PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-48P-M13 MQP-48C-P01 Package FPT-48P-M13 MQP-48C-P01 x x MB89P135A x MB89PV130A x x x x MB89121 MB89123A MB89125A MB89P133A MB89P131
: Available, x : Not available
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the one-time ROM product, verify its difference from the product that will actually be used. Take particular care on the following points: * The number of register banks available is different between the MB89121 and the MB89123A/125A/P135A/ PV130A. * The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
* When operated at low speed, a product with an OTPROM (EPROM) will consume more current than a product with a mask ROM. However, the same is current consumption in the sleep/stop mode is the same. (For more information, see "s Electrical Characteristics.") * In the case of the MB89PV130A, added is the current consumed by the EPROM which is connected to the top socket.
3. Mask Options
Functions that can be selected as options and how to designate these options vary with product. Before using options, check "s Mask Options." Take particular care on the following point: * P40 to P43 must be set for no pull-up resistor optional when an A/D converter is used. * Options are fixed on the MB89PV130A. Note: Package details of OTPROM products and piggyback/evaluation products are common to those of MB89130/ 130A series. Refer to the MB89130/130A series data sheet for details.
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MB89120/120A Series
s PIN ASSIGNMENT
(Top view) P40 P41 P42 P43 AVR AVSS P30/SCK P31/SO P32/SI P33/EC/SCO P34/TO/INT0 P35/INT1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Note: Parenthesized function is available only for the MB89120A series.
P24 P23 P22 P21 P20 P17 VSS P16 P15 P14 P13 P12
13 14 15 16 17 18 19 20 21 22 23 24
AVCC RST MOD0 MOD1 X0 X1 VCC X0A X1A P27 P26 P25
1 2 3 4 5 6 7 8 9 10 11 12
P36/INT2 P37/BZ/(RCO) P00/(INT20) P01/(INT21) P02/(INT22) P03/(INT23) P04/(INT24) P05/(INT25) P06/(INT26) P07/(INT27) P10 P11
(FPT-48P-M13)
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MB89120/120A Series
s PIN DESCRIPTION
Pin no. 5 6 8 9 3 4 2 Pin name X0 X1 X0A X1A MOD0 MOD1 RST D C Operation mode select pins Connect these pins directly to VSS. Reset I/O pin This port is of N-ch open-drain output type with pull-up resistor and a hysteresis input type. The internal circuit is initialized by the input of "L". "L" is output from this pin by an internal reset source as optional setting. General-purpose I/O ports On the MB89120A series, these pins also serve as external interrupt input. External interrupt input is hysteresis input. General-purpose I/O ports General-purpose output-only ports General-purpose I/O port Also serves as clock I/O for the 8-bit serial I/O interface. This port is of hysteresis input type. General-purpose I/O port Also serves as a serial I/O data output. This port is of hysteresis input type. General-purpose I/O port Also serves as a serial I/O data input. This port is of hysteresis input type. General-purpose I/O port Also serves as the external clock input for the 8-bit timer/counter. This port is of hysteresis input type. System clock output is optional. General-purpose I/O port Also serves as the overflow output and external interrupt input for the 8-bit timer/counter. This port is of hysteresis input type. General-purpose I/O ports Also serve as an external interrupt input. These ports are of hysteresis input type. General-purpose I/O port Also serves as a buzzer output. This port is of hysteresis input type. On the MB89120A series, the pin also serves as a remote control output. B Subclock crystal oscillator pins (for 32.768 kHz) Circuit type A Function Main clock crystal oscillator pins (max. 4.2 MHz)
27 to 34
P07/(INT27) to P00/(INT20)
I
18, 20 to 26 10 to 17 42
P17 to P10 P27 to P20 P30/SCK
E G F
41
P31/SO
F
40
P32/SI
F
39
P33/EC/SCO
F
38
P34/TO/INT0
F
36, 37 35
P36/INT2, P35/INT1 P37/BZ/(RCO)
F
F
(Continued)
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MB89120/120A Series
(Continued)
Pin no. 45 to 48 7 19 1 44 43 Pin name P43 to P40 VCC VSS AVCC AVR AVSS Circuit type H -- -- -- -- -- Power supply pin Power supply (GND) pin Power supply (GND) pin Use this pin at the same voltage as VCC. Reference voltage input pin Power supply (GND) pin Use this pin at the same voltage as VSS. Function N-ch open-drain output ports
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MB89120/120A Series
s I/O CIRCUIT TYPE
Type Circuit
X1 X0
Remarks
A
* Crystal and ceramic oscillation type (main clock) * Cricuit for the MB89P133A/P131/P135A/PV130A * External clock input select versions of MB89121/ 123A/125A At an oscillation feedback resistor of approximately 1 M /5 V
Standby control signal
X1
X0
* Crystal and ceramic oscillation type (main clock) * Crystal or ceramic oscillator select versions of MB89121/123A/125A At an oscillation feedback resistor of approximately 1 M/5 V
Standby control signal
B
X1A
X0A
* Crystal and ceramic oscillation type (subclock) Circuit for the MB89121/123A/125A At an oscillation feedback resistor of approximately 4.5 M/5 V
Standby control signal X1A
X0A
* Crystal and ceramic oscillation type (subclock) Circuit for the MB89P131/P133A/P135A/PV130A At an oscillation feedback resistor of approximately 4.5 M/5 V
Standby control signal
C D
R P-ch
* Output pull-up resistor (P-ch) of approximately 50 k /5 V * Hysteresis input
N-ch
(Continued)
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MB89120/120A Series
(Continued)
Type Circuit Remarks
E
R P-ch P-ch
* CMOS output * CMOS input
N-ch
* Pull-up resistor optional F
R P-ch P-ch
* CMOS output * Hysteresis input
N-ch
* Pull-up resistor optional G
P-ch
* CMOS output
N-ch
H
R P-ch
* N-ch open-drain output
N-ch
* Pull-up resistor optional * CMOS output * CMOS input * The interrupt input is a hysteresis input (available only on the MB89120A series).
I
R
P-ch
N-ch
Interrupt input Only for the MB89120A series
* Pull-up resistor optional
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MB89120/120A Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high- voltage pins, or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly, and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS =AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and release from stop mode.
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MB89120/120A Series
s PROGRAMMING TO THE EPROM ON THE MB89P131
The MB89P131 is a one-time PROM version of the MB89121.
1. Features
* 4-Kbyte PROM on chip * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below:
Address 0000H I/O Not available RAM 0000H Not available F000H 7000H Not available Single chip EPROM mode (Corresponding addresses in the EPROM programmer)
PROM 4 KB
EPROM 32 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode the MB89P131 functions equivalent to the MBM27C256A. This allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. Note, however, that the electronic signature mode cannot be used. * Programming procedure (1) Set the EPROM programmer to MBM27C256A. (2) Load program data into the EPROM programmer at 7000H to 7FFFH (note that addresses F000H to FFFFH while operating as a single chip correspond to 7000H to 7FFFH in EPROM mode). (3) Program with the EPROM programmer.
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MB89120/120A Series
s PROGRAMMING TO THE EPROM ON THE MB89P133A
The MB89P133A is a one-time PROM version of the MP89123A.
1. Features
* 8-Kbyte PROM on chip * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below:
Address 0000H I/O RAM 0000H Not available Single chip EPROM mode (Corresponding addresses in the EPROM programmer)
Not available
E000H PROM 8 KB
6000H EPROM 32 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode the MB89P133A functions equivalent to the MBM27C256A, This allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. Note, however, that the MB89P133A cannot use the electronic signature mode. * Programming procedure (1) Set the EPROM programmer to MBM27C256A. (2) Load program data into the EPROM programmer at 6000H to 7FFFH (note that addresses E000H to FFFFH while operating as a single chip correspond to 6000H to 7FFFH in EPROM mode). (3) Program with the EPROM programmer.
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MB89120/120A Series
s PROGRAMMING TO THE EPROM ON THE MB89P135A
The MB89P135A is an OTPROM version of the MB89133A/135A.
1. Features
* 16-Kbyte PROM on chip * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address 0000 H
Single chip
EPROM mode (Corresponding addresses on the EPROM programmer)
I/O 0080 H RAM 0280 H Not available 8000 H Not available BFF0 H Not available BFF6 H Not available C000H 4000 H 3FF6H Vacancy (Read value FFH) 3FF0 H Option area 0000 H Vacancy (Read value FFH)
PROM 16 KB
EPROM 16 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P135A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. * Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a single chip correspond to 4000H to 7FFFH in EPROM mode). (3) Load option data into the EPROM programmer at 3FF0H to 3FF6H. (4) Program with the EPROM programmer. 13
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MB89120/120A Series
4. Setting OTPROM Options (MB89P135A Only)
The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: * OTPROM option bit map Address 3FF0H Bit 7 Vacancy Bit 6 Vacancy Bit 5 Vacancy Bit 4 Bit 3 Reset pin output 1: Yes 0: No P03 Pull-up 1: Yes 0: No P13 Pull-up 1: Yes 0: No P33 Pull-up 1: Yes 0: No Vacancy Bit 2 Power-on reset 1: Yes 0: No P02 Pull-up 1: Yes 0: No P12 Pull-up 1: Yes 0: No P32 Pull-up 1: Yes 0: No Vacancy Bit 1 Bit 0
Clock mode selection Readable and Readable and Readable and 1: Single clock writable writable writable 0: Dual clock P07 Pull-up 1: Yes 0: No P17 Pull-up 1: No 0: Yes P37 Pull-up 1: Yes 0: No Vacancy P06 Pull-up 1: Yes 0: No P16 Pull-up 1: No 0: Yes P36 Pull-up 1: Yes 0: No Vacancy P05 Pull-up 1: Yes 0: No P15 Pull-up 1: Yes 0: No P35 Pull-up 1: Yes 0: No Vacancy P04 Pull-up 1: Yes 0: No P14 Pull-up 1: Yes 0: No P34 Pull-up 1: Yes 0: No Vacancy
Oscillation stabilization time 00: 24/FCH 01: 212/FCH P01 Pull-up 1: Yes 0: No P11 Pull-up 1: Yes 0: No P31 Pull-up 1: Yes 0: No Vacancy 10 : 216/FCH 11: 218/FCH P00 Pull-up 1: Yes 0: No P10 Pull-up 1: Yes 0: No P30 Pull-up 1: Yes 0: No Vacancy
3FF1H
3FF2H
3FF3H
3FF4H
Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and writable writable writable writable writable writable writable writable Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy
3FF5H
Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and writable writable writable writable writable writable writable writable Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy
3FF6H
Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and writable writable writable writable writable writable writable writable
Note: Each bit is set to `1' as the initialized value, therefore the pull-up option is not selected.
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MB89120/120A Series
s HANDLING MB89P131/P133A
1. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
2. Programming Yield
Due to its nature, bit programming test can't be conducted as Fujitsu delivery test. For this reason, a programming yeild of 100% cannot be assured at all times.
3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Recommended programmer manufacturer and programmer name Minato Electronics Inc. 1890A MB89P131PF MB89P133APFM QFP-48 ROM-48QF2-28DP-8L Recommended --
Part no.
Package
Compatible socket adapter Sun Hayato Co., Ltd.
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Minato Electronics Inc.: TEL: USA (1)-916-348-6066 JAPAN (81)-45-591-5611
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MB89120/120A Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below: Package LCC-32(Square) Adapter socket part number ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM is diagrammed below.
Address 0000H
Single chip
Corresponding addresses on the EPROM programmer
I/O 0080H RAM 0480H Not available 8000H 0000H
PROM 32 KB
EPROM 32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer for the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program with the EPROM programmer.
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MB89120/120A Series
s BLOCK DIAGRAM
X0 X1
Main clock oscillator
Timebase timer
Clock controller X0A X1A Subclock oscillator (32.768 kHz) Internal bus
Reset circuit (WDT)
RST
8-bit timer/counter
P34/TO/INT0
CMOS I/O port Port 0/1 P00/(INT20) to 8 P07/(INT27) 8 P10 to P17
8-bit timer/counter External interrupt (Wake-up) 8-bit serial I/O Port 3
P33/EC/SCO
P30/SCK P32/SI P31/SO
External interrupt
P20 to P27
8
Port 2
P35/INT1 Remote control transmission frequency CMOS output port Buzzer output CMOS I/O port P36/INT2
P37/BZ/(RCO)
RAM
N-ch open-drain output port Port 4 4 P40 to P43
F M C- 8L CPU
2
RO M
The other pins MOD0, MOD1, VCC, VSS AVCC, AVR, AVSS
: Only the MB89120A series has wake-up interrupt inputs and remote control transmission. Note: Parenthesized pins are available only with the MB89120A series.
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MB89120/120A Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89120/A series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/ O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is allocated from exactly the opposite end of I/O area, that is, near the highest address. The tables of interrupt reset vectors and vector call instructions are allocated from the highest address with the program area. The memory space of the MB89120/A series is structured as illustrated below: Memory Space
MB89121 MB89P131 0000H I/O 007FH 0080H Not available 00BFH 00C0H 0100H Register 013FH 0140H 017FH 0180H 007FH 0080H 0000H
MB89123A MB89P133A 0000H I/O 007FH 0080H RAM 0100H Register 017FH 0180H Not available 0100H
MB89125A
MB89P135A
MB89PV130A
0000H I/O 007FH 0080H RAM 00FFH 0100H Register 01FFH 0200H 027FH 0280H Vacancy BFFFH C000H Register RAM 512 B I/O
0000H I/O 007FH 0080H RAM 1 KB 00FFH 0100H Register 01FFH 0200H 047FH 0480H 7FFFH 8000H
RAM
Not available BFFFH C000H
Vacancy
Not available DFFFH E000H EFFFH F000H ROM FFFFH FFFFH ROM
ROM
ROM 16 KB
External ROM 32 KB
FFFFH
FFFFH
FFFFH
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MB89120/120A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated hardware registers and general-purpose memory registers. The following dedicated registers are provided:
Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS):
A 16-bit-long register for indicating the instruction storage positions A 16-bit-long temporary register for arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit-long register which is used for arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit-long register for index modification A 16-bit-long pointer for indicating a memory address A 16-bit-long pointer for indicating a stack area A 16-bit-long register for storing a register pointer, a condition code
16 bits PC A T IX EP SP PS : Program counter : Accumulator
Initial value FFFDH Indeterminate
: Temporary accumulator Indeterminate : Index register : Extra pointer : Stack pointer : Program status Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are Indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) (see the diagram below).
Structure of the Program Status Register
15 PS
14
13 RP
12
11
10
9
8
7 H
6 I
5
4
3 N
2 Z
1 V
0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
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MB89120/120A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and bits for control of CPU operations at the time of an interrupt. H-flag: Set to `1' when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared `0' otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is enabled when this flag is set to `1'. Interrupt is disabled when the flag is cleared to `0'. Cleared to `0' at the reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit.
IL1 0 0 1 1
IL0 0 1 0 1
Interrupt level 1 2 3
High-low High
Low
N-flag: Set to `1' if the MSB becomes `1' as the result of an arithmetic operation. Cleared to `0' otherwise. Z-flag: V-flag: Set to `1' when an arithmetic operation results in 0. Cleared to `0' otherwise. Set to `1' if the complement on `2' overflows as a result of an arithmetic operation. Cleared to `0' if the overflow does not occur.
C-flag: Set to `1' when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to `0' otherwise. Set to the shift-out value in the case of a shift instruction.
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MB89120/120A Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit-long register for storing data The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 8 banks can be used on the MB89121/P131, and a total of 16 banks can be used on the MB89123A/125A/P133A and a total of 32 banks can be used on the MB89135A/PV130A. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuraiton
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 8 banks (MB89121/P131) 16 banks (MB89123A/125A/133A) 32 banks (MB89P135A/PV130A)
Memory area
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MB89120/120A Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) T2CR T1CR T2DR T1DR SMR1 SDR1 (R/W) (R/W) RCR1 RCR2 (R/W) SCGC (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) SYCC STBC WDTC TBTC WPCR PDR3 DDR3 PDR4 BZCR Read/write (R/W) (W) (R/W) (W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register Vacancy Vacancy System clock control register Standby control register Watchdog control register Time-base timer control register Watch prescaler control register Port 3 data register Port 3 data direction register Port 4 data register Buzzer register Vacancy Vacancy Peripheral control clock register Vacancy Remote control transmission control register 1* Remote control transmission control register 2* Vacancy Vacancy Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register Serial mode register Serial data register Vacancy Vacancy
(Continued)
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MB89120/120A Series
(Continued)
Address 20H 21H 22H 23H 24H 25H 26H to 31H 32H 33H 34H to 7BH 7CH 7DH 7EH 7FH * : Only in the MB89120A series Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) EIE2 EIF2 (R/W) (R/W) EIC1 EIC2 Read/write Register name Vacancy Vacancy Vacancy External interrupt control register 1 External interrupt control register 2 Vacancy Vacancy External interrupt 2 enable register* External interrupt 2 flag register* Vacancy Interrupt level register 1 Interrupt level register 2 Interrupt level register 3 Vacancy Register description
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MB89120/120A Series
s ELECTRICAL CARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC AVR VPP VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Value Min. VSS - 0.3 Max. VSS + 7.2 Unit Remarks Use VCC, AVCC , and AVR set to the same voltage. MOD1 pin on the MB89P131/P133A/ P135A
Power supply voltage
V
Program voltage Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
VSS - 0.6 VSS - 0.3 VSS - 0.3 -40 -55
VSS + 13.0 VCC + 0.3 VCC + 0.3 10 4 100 20 -10 -2 -30 -10 200 +85 +150
V V V mA mA mA mA mA mA mA mA mW C C
Avarage value (operating current x operating rate)
Avarage value (operating current x operating rate) Avarage value (operating current x operating rate)
Avarage value (operating current x operating rate)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB89120/120A Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V) Parameter Symbol Value Min. 2.2* VCC AVCC AVR Max. 6.0* Unit Remarks Normal operation assurance range* for MB89121/123A/125A Normal operation assurance range* for MB89P131/P133A/ P135A/PV130A Retains the RAM state in stop mode
V
Power supply voltage
2.7*
6.0*
V
1.5 Operating temperature TA -40
6.0 +85
V C
* : These values vary with the operating conditions. See Figures 1 and 2. Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MB89P131/P133A/P135A/PV130A, and single-clock MB89121/123A/125A)
6
Operating voltage (V)
5 Operation assurance range 4
3
2
1
1
2
3
4
Main clock oprating frequency (Instruction cycle time of 4/FCH) (MHz)
4.0 Minimum execution time (s)
2.0
1.0
Note: The shaded area is assured only for the MB89121/123A/125A (instruction cycle time of 4/FCH).
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MB89120/120A Series
Figure 2
Operating Voltage vs. Main Clock Operating Frequency (Dual-clock MB89121/123A/125A)
6
Operating voltage (V)
5
4 Operation assurance range 3
2
1
1
2
3
4
Main clock operating frequency (Instruction cycle time of 4/FCH) (MHz) 4.0 Minimum execution time (s) 2.0 1.0
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
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MB89120/120A Series
3. DC Characteristics
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. 0.7 VCC VCC + 0.3 V INT20 to INT27 are available only in the MB89120A series.
Parameter
Symbol VIH
Pin P00 to P07, P10 to P17 RST, P30 to P37, INT20 to INT27 P00 to P07, P10 to P17 RST, P30 to P37, INT20 to INT27
"H" level input voltage
VIHS
0.8 VCC
VCC + 0.3
V
VIL "L" level input voltage
VSS - 0.3
0.3 VCC
V INT20 to INT27 are available only in the MB89120A series.
VILS
VSS - 0.3
0.2 VCC
V
Open-drain output pin applied voltage "H" level output voltage
VD
P40 to P43 P00 to P07, P10 to P17, P20 to P27, P30 to P37 P00 to P07, P10 to P17 P20 to P27, P30 to P37, P40 to P43 RST P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P43, MOD0, MOD1 P00 to P07, P10 to P17, P30 to P37, P40 to P43, RST
VSS - 0.3
VCC+ 0.3
V
VOH
IOH = -2.0 mA
2.4
V
"L" level output voltage
VOL
IOL = 1.8 mA

0.4
V
VOL2 Input leakage current (Hi-z output leakage current)
IOL = 4.0 mA
0.6
V Without pull-up resistor
ILI
0.45 V < VI < VCC
5
A
Pull-up resistance
RPULL
VI = 0.0 V
25
50
100
k
(Continued)
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MB89120/120A Series
(Continued)
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. VCC = 5.0 V FCH = 4.00 MHz tinst*2 = 1.0 s VCC = 5.0 V FCH = 4.00 MHz Main sleep mode tinst*2 = 1.0 s VCC = 3.0 V FCL = 32.768 kHz Subclock mode VCC (External clock operation) VCC = 3.0 V FCL = 32.768 kHz Subclock sleep mode VCC = 3.0 V FCL = 32.768 kHz * Watch mode * Main clock stop mode at dual clock system TA = +25C * Subclock stop mode * Main clock stop mode at single clock system Other than AVCC, AVSS, f = 1 MHz VCC, and VSS -- -- 4 6 7 10 mA mA MB89121/ 123A/125A MB89P131/ P133A/P135A
Parameter
Symbol
Pin
ICC1
ICCS1
--
2
5
mA
-- --
50 1
100 3
A mA
ICCL
MB89121/ 123A/125A MB89P131/ P133A/P135A
Power supply current*1
ICCLS
--
25
50
A
ICCT
--
--
15
A
ICCH
--
--
1
A
Input capacitance CIN
--
10
--
pF
*1: The measurement conditions of power supply current is external clock. *2: For information on tinst, see "(4) Instruction Cycle" in "4 AC Characteristics."
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MB89120/120A Series
4. AC Characteristics
(1) Reset Timing (VCC = +5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter RST "L" pulse width Symbol tZLZH Condition -- Value Min. 48 tHCYL* Max. -- Unit ns Remarks
* : tHCYL is the oscillation cycle (1/FCH) input to the X0.
tZLZH RST 0.2 VCC 0.8 VCC 0.2 VCC
(2) Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Condition Value Min. -- -- Power supply cut-off time tOFF 1 -- ms Max. 50 Unit Remarks Power-on reset function only Due to repeated operations
Power supply rising time
tR
ms
Note: Make sure that power supply rises within the oscillation stabilization time selected. When the main clock is operating at FCH = 3 MHz and the oscillation stabilization time select option has been set to 212/FCH, for example, the oscillation settling time is 1.4 ms and accordingly the maximum value of power supply rising time is about 1.4 ms. Keep in mind that rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.0 V 0.2 V 0.2 V
tOFF
VCC
0.2 V
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MB89120/120A Series
(3) Clock Timings (VSS = 0.0 V, TA = -40C to +85C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FCH FCL tHCYL tLCYL PWH1 PWL1 tCR1 tCF1 Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0 Value Min. 1 -- 238 -- 72 -- Typ. -- 32.768 -- 30.5 -- -- Max. 4.2 -- 1000 -- -- 24 Unit MHz kHz ns s ns ns Remarks Main clock Subclock Main clock Subclock External clock External clock
X0, X1 Timings and Conditions of Applied Voltage
tHCYL 0.8 VCC 0.2 VCC
X0
PWH1
PWL1 tCF1
tCR1
Main Clock Conditions
When a crystal or ceramic resonator is used X0 X1
When an external clock is used X0 X1
FCH C0 C1 FCH
Open
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MB89120/120A Series
X0A, X1A Timings and Conditions of Applied Voltage
tLCYL 0.8 VCC
X0A
Subclock Conditions
When a crystal or ceramic resonator is used X0A X1A
Single-clock option is used X0A X1A
Rd
Open
FCL C0 C1
(4) Instruction Cycles (VSS = 0.0 V, TA =-40C to +85C) Parameter Instruction cycle (minimum execution time) Symbol Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL s Unit s Remarks (4/FCH) tinst = 1.0 s when operating at FCH = 4 MHz tinst = 61.036 s when operating at FCL = 32.768 kHz
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MB89120/120A Series
(5) Recommended Resonator Manufacturers Sample Application of Piezoelectric Resonator (FAR Series) for Main Clock Oscillation Circuit
X0
X1 R FAR1
C12
C22 1: Fujitsu Acoustic Resonator
FAR part number Frequency Dumping (built-in capacitor type) (MHz) resistor 1000 510 --
Initial deviation of FAR frequency (TA = +25C)
Temperature Loading characteristics of FAR frequency capacitors*2 (TA = -20C to +60C)
FAR-C4CC-02000-L00 FAR-C4 A-03580- 01 FAR-C4CB-04000-M00 Inquiry: FUJITSU LIMITED
2.00 3.58 4.00
0.5%
0.5%
Built-in
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MB89120/120A Series
Sample Application of Ceramic Resonator for Main Clock Oscillation Circuit
X0
X1 R
C1
C2
* Mask ROM products Resonator manufacturer* Kyocera Corporation Matsushita Electronic Components Resonator KBR-4.0MKS EFOV4004B CSBF1000J Murata Mfg. Co. Ltd. CSTCS4.00MG800 CSA4.00MG040 CST4.00MGW040 Inquiry: Kyocera Corporation * AVX Corporation North American Sales Headquarters: TEL (803) 448-9411 * AVX Limited European Sales Headquarters: TEL (01252) 770000 * AVX/Kyocera H.K. Ltd. Asian Sales Headquarters: TEL 363-3303 Matsushita Electronic Components Co., Ltd. * Ceramic Division: TEL 81-6-908-1101 Murata Mfg Co., Ltd. * Murata Electronics North America, Inc.: TEL 1-404-436-1300 * Murata Europe Management GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233 4.00 Frequency (MHz) 4.00 4.00 1.00 C1 (pF) 33 Built-in 100 Built-in 100 Built-in C2 (pF) 33 Built-in 100 Built-in 100 Built-in R Not required 1.5 k 6.8 k Not required Not required Not required
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MB89120/120A Series
Sample Application of Crystal Resonator for Subclock Oscillation Circuit
X0A
X1A Rd
C1
C2
* Mask ROM product Resonator manufacturer* SII Resonator DS-VT-200 Frequency (kHz) 32.768 C1 (pF) 24 C2 (pF) 24 Rd 680 k
Inquiry: SII * Seiko Instruments Inc. (Japan): TEL 81-43-211-1219 * Seiko Instruments U.S.A. Inc.: TEL 310-517-7770 * Seiko Instruments GmbH: TEL 49-6102-297-122
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MB89120/120A Series
(6) Serial I/O Timings (VCC = +5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Serial clock cycle time SCK SO time Valid SI SCK SCK Valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK SCK Valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK SCK, SO SI, SCK SCK, SI SCK SCK, SO SI, SCK SCK, SI External clock operation Internal clock operation Condition Value Min. 2 tinst* -200 200 200 tinst* tinst* 0 200 200 Max. -- 200 -- -- -- -- 200 -- -- Unit s ns ns ns s s ns ns ns Remarks
* : For information on tinst, see "(4) Instruction Cycles." Internal Shift Clock Mode
tSCYC
SCK
2.4 V 0.8 V 0.8 V
tSLOV
SO
2.4 V 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SI
0.2 VCC
External Shift Clock Mode
tSLSH tSHSL 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC
SCK
tSLOV
SO
2.4 V 0.8 V
tIVSH 0.8 VCC
tSHIX 0.8 VCC 0.2 VCC
SI
0.2 VCC
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MB89120/120A Series
(7) Peripheral Input Timings (VCC = +5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width Symbol tILIH tIHIL Pin EC, INT0 to INT2 Value Min. 2 tinst* 2 tinst* Max. -- -- Unit s s Remarks
* : For information on tinst, see "(4) Instruction Cycle."
tIHIL EC INT0 to 2 0.8 VCC 0.2 VCC 0.2 VCC
tILIH
0.8 VCC
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MB89120/120A Series
s EXAMPLE CHARACTERISTICS
(1) "L" Level Output Voltage
VOL vs. IOL
VOL (V) 1.1 TA = +25C VCC = 2.2 V 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 1 2 345 VCC = 2.5 V VCC - VOH (V) VCC = 2.2 V 1.1 TA = +25C 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 -.5 -1.0 -1.5 -2.0 VCC = 2.5 V
(2) "H" Level Output Voltage
VCC - VOH vs. IOH
VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
6
7
8
9
10 IOL (mA)
-2.5
-3.0 IOH (mA)
(3) "H" Level Input Voltage/"L" Level Input Voltage (CMOS Input)
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 .00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 VCC (V)
(4) "H" Level Input Voltage/"L" Level Input Voltage (Hysteresis Input)
VIN (V) 5.0 4.5 TA = +25C 4.0 VIHS 3.5 3.0 2.5 2.0 VILS 1.5 1.0 0.5 0 .00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level
VIN vs. VCC
VIN vs. VCC
TA = +25C
(5) Pull-up Resistance
RPULL (k) 1000
RPULL vs. VCC
TA = +25C
300
100 50
10 0 1 2 3 4 5 6 7 VCC (V)
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MB89120/120A Series
(6) Power Supply Current
ICC1 vs. VCC
ICC (mA) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) Divide by 64 1.5 1.0 0.5 FCH = 4.0 MHz TA = +25C Divide by 4 (ICC1) ICCS (mA) 3.0 2.5 2.0 Divide by 64 FCH = 4.0 MHz TA = +25C Divide by 4 (ICCS1)
ICCS1 vs. VCC
ICCL vs. VCC
ICCL (A) 200 180 160 140 120 100 80 60 40 20 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) TA = +25C VCCLS (A) 50 45 40 35 30 25 20 15 10 5
ICCLS vs. VCC
TA = +25C
0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V)
ICCT vs. VCC
ICCT (A) 30 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) ICCH (A) 2.0 TA = +25C 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.0 2.5 3.0 3.5
ICCH vs. VCC
TA = +25C
4.0
4.5
5.0
5.5
6.0
6.5 VCC (V)
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MB89120/120A Series
s INSTRUCTIONS
Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others
Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Meaning
(Continued)
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MB89120/120A Series
(Continued)
Symbol EP PC SP PS dr CCR RP Ri x (x) (( x )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents at address `x' is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents at address `x' is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning
Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction The number of instructions The number of bytes Operation of an instruction A changed content of the TL, TH and AH when instruction is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH preceding the instruction executed. * 00 becomes 00. N, Z, V, C: OP code: Flags of the condition code register. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F.
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MB89120/120A Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ((EP)) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ((IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
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MB89120/120A Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 Arithmetic Operation Instructions (62 instructions) # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) C A CA (A) -d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
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MB89120/120A Series
(Continued)
Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 TL - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - - NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Table 1 Branch Instructions (17 instructions) Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Operation If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N= 1 then PC PC + rel If V N= 0 then PC PC + reI If (dir: b)= 0 then PC PC + rel If (dir: b)= 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
Table 1 The Other Instructions (9 instructions) Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ 4 4 4 4 1 1 1 1 1 # 1 1 1 1 1 1 1 1 1 Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
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MB89120/120A Series
s INSTRUCTION MAP
L 0 1 2 3 4 5 6 7 8 9 A B C D E F
H
0 NOP MULU A ROLC A RORC A
1 SWAP DIVU A CMP A CMPW A
2 RET
3 RETI
4 PUSHW A
5 POPW A
6 MOV A,ext
7
8
9 SETI SETC
A
B
C
D
E
F
MOVW CLRI A,PS
CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A ADDC A ADDCW A SUBCW A SUBC A XCH A, T XOR A AND A OR A A
MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP DAS CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
XCHW XORW ANDW ORW A, T A A
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 MOV A,dir CMP A,dir
XOR AND OR DAA A,#d8 A,#d8 A,#d8
ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP
CMP CLRB BBC MOVW MOVW MOVW XCHW MOV CMP ADDC SUBC MOV XOR AND OR MOV dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A @A,IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 MOV CMP ADDC SUBC MOV XOR AND OR MOV A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 MOV A,R0 MOV A,R1 MOV A,R2 MOV A,R3 MOV A,R4 MOV A,R5 MOV A,R6 MOV A,R7 CMP A,R7 CMP A,R6 CMP A,R5 CMP A,R4 CMP A,R3 CMP A,R2 CMP A,R1 CMP A,R0 CMP @EP,#d8 CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 CALLV #7 R5 CALLV #6 BLT rel R4 CALLV #5 BGE rel R3 CALLV #4 BZ rel R2 CALLV #3 BNZ rel R1 CALLV #2 BN rel R0 CALLV #1 BP rel CALLV #0 BC rel BNC rel
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
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MB89120/120A Series
s MASK OPTIONS
Part number No. Specifying procedure MB89121 MB89123A MB89125A Specify when ordering masking MB89P131 MB89P133A Specify when ordering masking MB89P135A Set with EPROM programmer MB89PV130A Specification impossible
1
Selectable by pin (P40 to P43 are Pull-up resistors * P00 to P07, P10 to P17, Selectable by pin available for no pullup resistors when an * P30 to P37, P40 to P43 A/D converter is used.) Power-on reset * Power-on reset provided Selectable * No power-on reset Selection of oscillation stabilization wait time * The oscillation stabilization wait time initial value is selectable from 4 types given below. 0: Oscillation stabilization 24/FCH 1: Oscillation stabilization 212/FCH 2: Oscillation stabilization 216/FCH 3: Oscillation stabilization 218/FCH Reset pin output * Reset output provided * No reset output Clock mode selection * Single-clock mode * Dual-clock mode Main clock oscillation circuit type * External clock input * Oscillation resonator Peripheral control clock output function*2 * Not used * Used Selectable
Selectable by pin All pins fixed to (P40 to P43 must no pull-up resistor be set to without optional a pull-up resistor.)
2
Selectable
With power-on reset
3
Selectable
Selectable
Selectable
Oscillation stabilization 218/FCH
4
Selectable
Selectable
Selectable
With reset output
5
Selectable
Selectable
Selectable
Dual-clock mode
6
Selectable
Not required*1
7
Selectable
Not required*3
*1: Both external clock and oscillation resonator is usable on the one-time product. *2: "Used" must be selected when P33 (39 pin) is used as SCO for the peripheral control clock output. *3: The peripheral control clock function can be used only by software.
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MB89120/120A Series
s MB89P131/P133A STANDARD OPTIONS
No. 1 2 3 4 5 Product option Pull-up resistor Power-on reset Selection of oscillation stabilization time Reset pin output Clock mode selection MB89P131-101 Not provided for any port Provided
16
MB89P133A-201 Not provided for any port Provided
2: Oscillation stabilization 2 /FCH 2: Oscillation stabilization 216/FCH Provided Dual-clock mode Provided Dual-clock mode
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MB89120/120A Series
s ORDERING INFORMATION
Part number MB89121PFM MB89123APFM MB89125APFM Package 48-pin Plastic QFP (FPT-48P-M13) Remarks
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MB89120/120A Series
s PACKAGE DIMENSIONS
48-pin Plastic QFP (FPT-48P-M13)
13.100.40 SQ (.516.016) 10.000.20 SQ (.394.008)
36 25
2.35(.093)MAX 0(0)MIN (STAND OFF)
37
24
Details of "A" part 0.15(.006) 8.80 (.346) REF
11.500.30 (.453.012)
0.20(.008) 0.18(.007)MAX 0.53(.021)MAX
INDEX "A"
48 13
Details of "B" part LEAD No.
1 12
0.80(.0315)TYP
0.300.10 (.012.004) "B"
0.16(.006)
M
0.150.05 (.006.002) 0~10 0.800.30 (.031.012)
0.10(.004)
C
1994 FUJITSU LIMITED F48023S-1C-1
Dimensions in mm (inches)
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MB89120/120A Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED Printed in Japan
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